1. Field of the Invention
The present invention relates to an internal clock synchronizing method and circuit for synchronizing the internal clock signals used in a plurality of system component circuits constituting a system.
2. Description of Related Art
It is often necessary for a conventional system constructed by combining a plurality of system component circuits to synchronize their internal clock signals with each other. This is because the system component circuits are operating in synchronism with each other, and hence if their internal clock signals are brought out of synchronization, they cannot achieve smooth data exchange between them, which may lead to an erroneous operation.
Furthermore, to keep with the present trend to lower power consumption, the system component circuits are often provided with a function of reducing current consumption by halting their internal clock signals while they are inactive. This makes it necessary for these circuits to synchronize their internal clock signals again when they resume their operation.
Moreover, although clock generators of the system component circuits are conventionally synchronized with each other through an external reset or interrupt, the trend of devices toward a faster operating speed makes it difficult to establish accurate synchronization depending on the external reset timings.
One of such conventional internal clock synchronizing circuits is disclosed in Japanese patent application laid-open No. 62-118417/1987. It discloses a system consisting of multiple microprocessors (system component circuits), each of which generates its own divided clock signal (internal clock signal) by dividing a common original clock signal, and operates in synchronism with the divided clock. A phase comparator compares a pair of the divided clock signals generated by a pair of the microprocessors, and outputs a signal proportional to a phase difference between them. An integrator integrates the signal, and a comparator makes a decision whether the integral of the signal exceeds a reference value or not, and outputs a signal if the integral exceeds the reference value. Thus, if a decision is made that the phase difference occurs between the pair of the microprocessors, the supply of the original clock signal to one of the microprocessors is suspended until the phase difference is eliminated. Thus, the division of the original clock signal is suspended during that period. When the phase difference is cancelled out, the supply of the original clock signal is resumed along with the phase comparison.
Although the conventional internal clock synchronizing circuit with such an arrangement can achieve the synchronization of the internal clock signals (divided clock signals) between the system component circuits (microprocessors), it has a drawback that it takes a rather long time to establish the synchronization because it integrates the phase compared result, and then compares the integral results by the comparator to suspend the original clock signal. This present a problem of delaying the response in today's high speed microprocessors.